 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Technical Data Sheet Features SSC P485 PL Transceiver IC 4MHZ 1 2 3 4 5 6 7 8 9 10 20 19 18 17 VSSD TP0 VDDA SI C1 C2 SO VSSA RST* TS* * * * * * * Enables low-cost networking products Spread Spectrum CarrierTM communication technology 9600 baud data rate Simple interface Single +5 Volt power supply requirement 20 pin SOIC package NC VSSD XIN XOUT VDDD ILD DI RO WL SSC P485 16 15 14 13 12 11 Introduction The Intellon SSC P485 PL Transceiver IC is a highly integrated spread spectrum communication transceiver for implementing low-cost networking products. The SSC P485 contains a Spread Spectrum CarrierTM (SSC) transceiver, signal conditioning circuitry, and a simple host interface. A minimum of external circuitry is required to connect the SSC P485 to the DC power line, twisted pair cable, or other communication medium. The inherent reliability of SSC signaling technology provides substantial improvement in network and communication performance over other low-cost communication methods. The SSC P485 is the ideal basic communications element for a wide variety of low-cost networking applications. SSC P485 Block Diagram RST* ILD RO RX Interface Logic Data Decode Logic Tracking & Data Extraction Logic WL Summation Encoder Binary Shift Register C2 C1 Comp Amp SI SO DI TX Interface Logic Waveform Generator DAC Buf 4 MHz XIN XOUT Clock Circuit TS Control TS* July 1998 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC Absolute Maximum Ratings (1) Symbol VDDMAX VIN TSTG TL Parameter DC Supply Voltage Input Voltage at any Pin Storage Temperature Lead Temperature (Soldering, 10 seconds) Value -0.3 to 7.0 VSS-0.3 to VDD+0.3 -65 to +150 300 Unit V V C C Notes: 1. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions Symbol VDD FOSC TA Parameter DC Supply Voltage Oscillator Frequency Operating Temperature Humidity (non-condensing) Min 4.5 -40 Typical 5.0 12 0.05% +25 Max 5.5 +85 95 Unit V MHz C % Electrical Characteristics Conditions: VDD = 4.5 to 5.5 V T= -40 to +85C Symbol VOH VOL VIH VIL IIL vSO IDD Parameter Minimum High-level Output Voltage Maximum Low-level Output Voltage (1) Minimum High-level Input Voltage Maximum Low-level Input Voltage Maximum Input Leakage Current SSC Signal Output Voltage (2) Total Power Supply Current Min 2.4 2.0 Typical Max 0.4 0.8 10 Units V V V V A VP-P mA 4 15 Notes: 1. TS* pin IOL = 4 mA, all other outputs IOL = 2 mA 2. ZL = 2K || 10 pF July 1998 2 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC SSC P485 Pin Assignments Pin 1 2 3 4 5 6 7 Mnemonic 4MHZ NC VSSD XIN XOUT VDDD ILD Name 4 MHz Clock Out No Connect Digital Ground Crystal Input Crystal Output Digital Supply Idle Line Detect Description 4 MHz clock output available for host microcontroller. Digital ground reference. Connected to external crystal to excite the IC's internal oscillator and digital clock. Connected to external crystal to excite the IC's internal oscillator and digital clock. 5.0 VDC 10% digital supply voltage with respect to VSSD. Digital output, active high. Logic 1 state indicates 10 bit times of idle line, logic 0 indicates detection of carrier or non-idle line. Digital input. After the preamble, a low on DI (SPACE) transmits a superior2 state on SO, a high on DI (MARK) transmits a superior1 state on SO. Digital output. After the preamble and assuming standard polarity: if superior1 state is detected on SI, RO will be high (MARK), if superior2 state is detected on SI, RO will be low (SPACE). Digital input. Logic 1 (default, internal pullup) selects 10-bit frame (START, eight data bits, STOP), logic 0 selects 11-bit frame (START, nine data bits, STOP). Active low digital output. Enables the external output amplifier when driven high. Tri-states the external output amplifier when driven low. Active low digital input. RST* asynchronously forces RO and ILD outputs to a high state and TS* to a low state. RST* can be asserted anytime during normal operation to force the reset state. RST* must be active (low) for 1 sec after VDDD and VDDA stabilize and the crystal oscillator stabilizes to guarantee the internal reset state. See Figure 10. Analog ground reference. Analog signal output. Tri-state enabled with internal signal. Connection for 680pF capacitor to ground. Connection for 680pF capacitor to ground. Analog signal input. 5.0 VDC 10% analog supply voltage with respect to VSSA. Reserved pin for testing. Digital ground reference. 8 DI Driver Input 9 RO Receiver Output 10 WL Word Length 11 TS* Tristate 12 RST* Reset 13 14 15 16 17 18 19 20 VSSA SO C2 C1 SI VDDA TP0 VSSD Analog Ground Signal Output Capacitor 2 Capacitor 1 Signal Input Analog Supply Test Point 0 Digital Ground July 1998 3 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC SSC P485 Application Examples The SSC P485 may be used in a wide variety of applications. A typical node connecting to the medium is shown in Figure 1. A gateway between an RS485 twisted pair network and a DC power line network is shown in Figure 2. A multi-point network application with gateways using the SSC P485 is illustrated in Figure 3. Figure 4 presents a host interface flow diagram showing the major steps necessary to transmit and receive messages using the P485 IC. Single W ire SSC P111 Power Line Media Interface WR DI SSC P485 PL Transceiver SO Microprocessor based Control Logic output filter medium coupler RD RO TS* SI input filter ILD Figure 1. SSC P485 Typical Node Transmit Enable #1 RXD #1 TXD #1 Twisted Pair Single W ire RS-485 Transceiver A TXRDY #1 D RXRDY #1 RD #1 W R #1 RXD #1 R RE* DE UART TXD #1 + B Microprocessor based Control Logic DATA 0-7 RD #2 W R #2 TXRDY #2 RXD #2 RXRDY #2 RO TXD #2 DI SSC P485 PL Transceiver SO output filter SSC P111 Power Line Media Interface medium coupler UART TS* SI input filter ILD ILD Figure 2. SSC P485 Gateway July 1998 4 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC P111 IC DC power line P111 IC host micro P485 IC P485 IC host micro gateway gateway RS485 IC gate way micro P111 IC P111 IC P485 IC P485 IC gate way micro RS485 IC RS485 device RS485 device RS485 device RS485 device RS485 device RS485 device Figure 3. SSC P485 Multi-point Network Application July 1998 5 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC Entry No message to transmit? Yes ILD==logic 1? Yes write 1st character to UART UART indicates receive character available? No Yes read character from UART Yes transmitted last character? Yes character transmitted==character received? No write next character to UART No Yes No UART indicates transmit buffer available? No ILD==logic 1? No Yes message has been transmitted store character in message No UART indicates receive character available? Yes read character from UART Yes UART indicates receive character available? No No process message Yes 1-1/2 char times of quiet since last character? Figure 4. Host Interface Flow Diagram July 1998 6 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC SSC P485 Power Line Interface Analog data is transferred between the communication medium and the SSC P485 over the Signal In (SI) and Signal Out (SO) pins (refer to Figure 5). When transmitting, SSC "chirps" from the SSC P485 SO pin are filtered by the output filter to remove harmonic energy (distortion) from the transmit signal and then amplified by the SSC P111 Power Line Media Interface IC. The SSC P111 is a high-efficiency amplifier and tri-state switch specifically designed for use in power line network systems. The amplifier is powered down and its output set to a high impedance condition when the SSC P485 TS* signal is logic low, isolating the amplifier from the receive circuitry and reducing node power consumption during receive operation. When the SSC P485 TS* signal is logic high, the communication signal is routed to the communication medium through the coupling circuit (capacitor or transformer). When receiving, the communication signal passes through the coupling circuit and is filtered by the bandpass input filter. The resulting signal is then applied to the SSC P485 SI pin for processing. Refer to the application reference shown in Figure 14. Single Wire SO Host micro with internal UART TXD DI P485 IC TS* RXD RO SI output filter P111 IC medium coupler input filter ILD ILD Figure 5. SSC P485 Medium Coupling SSC P485 Message Format The P485 requires the following message formatting: Start bits Data bits Stop bits Character gap Message gap Message length 1, logic low 8 or 9 (default 8) 1, logic high 0-4 bit times 12 bit times minimum 1 character minimum July 1998 7 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC Transmit/Receive Timing The SSC P485 timing with contention resolution is shown below. The P485 generates a preamble based on the first character of the message. Contention resolution requires that the first character of the message be unique among all possible transmitters in the network. If the channel is available and the transmitter wins contention, a tracking sync sequence followed by a retransmission of the first character occurs. The P485 also echoes the first character back to the host allowing the host to determine that the channel was available and to continue transmitting the message. If the channel was unavailable (the transmitter lost contention), the SO line is tristated and the first character of the received message is passed to the host. The host determines that the channel was not available (transmitted first character does not match received first character), and the host enters the receive message mode. Once the end of message is detected, the P485 drives ILD high after 10 bit times to allow all nodes to arbitrate properly. The end of packet condition is true when 5 consecutive ones are detected on DI following a stop bit. Figure 6 shows a contention resolution example for two contending transmitters, and Figure 7 shows the end of message sequence and the assertion of ILD. Refer to Figure 9 for preamble and data encoding. July 1998 8 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC Network Bit Time Tracking character 1 DI St 0 1 2 3 4 5 6 7 Sp 2 bit times character 2 St 0 1 2 3 4 5 6 7 Sp 2 bit times St 0 1 preamble SO S S2 S2 S2 S2 S2 S1 S1 sync S1 S1 S1 S2 S2 S1 character 1 S2 S1 S1 S2 S1 S2 S1 stuff S1 S1 S2 S2 S2 character 2 S1 S1 S1 S2 S1 S2 S1 S1 stuff S1 S1 S2 S2 preamble SI S S2 S2 S2 S2 S2 S1 S1 sync S1 S1 S1 S2 S2 S1 character 1 S2 S1 S1 S2 S1 S2 S1 stuff S1 S1 S2 S2 S2 character 2 S1 S1 S1 S2 S1 S2 S1 S1 stuff S1 S1 S2 S2 character 1 echoed RO St 0 1 2 3 4 5 6 7 Sp St character 2 received 0 1 2 3 4 5 6 7 Sp 2.5 bit times St ILD Transmitter #1 character 1 DI St 0 1 2 3 4 5 6 7 Sp preamble SO S S2 S2 preamble SI S S2 S2 S2 S2 S2 S1 S1 sync S1 S1 S1 S2 S2 S1 character 1 S2 S1 S1 S2 S1 S2 S1 stuff S1 S1 S2 S2 S2 character 2 S1 S1 S1 S2 S1 S2 S1 S1 stuff S1 S1 S2 S2 character 1 received RO St 0 1 2 3 4 5 6 7 Sp St character 2 received 0 1 2 3 4 5 6 7 Sp 2.5 bit times St ILD Transmitter #2 (Receiver) Figure 6. Contention Resolution Timing July 1998 9 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC character n-1 DI St 0 1 2 3 4 5 6 7 Sp St 0 1 character n 2 3 4 5 6 7 Sp character n-1 SO S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S2 S2 S1 character n S2 S1 S1 S2 S1 S2 S1 S1 stuff (end of msg) S1 S1 S1 S1 S1 character n-1 SI S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S2 S2 S1 character n S2 S1 S1 S2 S1 S2 S1 S1 stuff (end of msg) S1 S1 S1 S1 S1 character n-1 received RO St 0 1 2 3 4 5 6 7 Sp St 0 character n received 1 2 3 4 5 6 7 Sp 10 bit times ILD Transmitter (MARK hold) DI (tri-state) character n-1 SI S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S2 S2 S1 SO character n S2 S1 S1 S2 S1 S2 S1 S1 stuff (end of msg) S1 S1 S1 S1 S1 character n-1 received RO St 0 1 2 3 4 5 6 7 Sp St 0 character n received 1 2 3 4 5 6 7 Sp 10 bit times ILD Receiver Figure 7. End of Message Timing July 1998 10 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC Spread Spectrum Carrier TM TM Technology Spread Spectrum Carrier (SSC) Technology is a method of spread spectrum communications suitable for both point-to-point or carrier sense multiple access (CSMA) networks. Historically, spread spectrum communication systems have been used for secure communications and/or to overcome narrow-band impairments in the communications medium. Spread spectrum receivers generally require an initial period of time to synchronize with the carrier, so they have not been appropriate for CSMA networks. Spread Spectrum Carrier Technology is a method by which a series of short, self-synchronizing, frequency swept "chirps" act as a carrier. The chirps are always of the same known pattern and detectable by all of the nodes on the network. The chirp ranges in frequency from 100 to 400 kHz over a duration of 100 s. The chirp is swept from approximately 200 kHz to 400 kHz and then from 100 kHz to 200 kHz. Figure 8 illustrates the SSC power line chirp. Figure 8. Spread Spectrum Carrier Chirp Preamble Encoding Two modulation schemes are used for symbol transmission by the physical layer. Amplitude Shift Keying (ASK) is used in the preamble of the message packet. ASK modulation uses SUPERIOR and INFERIOR states to encode symbols. A SUPERIOR state is represented by the presence of a chirp and an inferior state by the absence of a chirp. Because the transmitter is quiet during inferior states, superior states transmitted by other devices contending for the channel can be detected during the preamble of the packet. An example of ASK modulation is shown in Figure 9. Note that in the preamble, the duration of a symbol is slightly longer than in the body of the packet. A preamble symbol is 114 s in length. Symbols in the sync sequence and the Packet Body are 100 s in length. Please note the "Chirp" is ALWAYS 100s in length and is followed by 14 s of quiet time during the preamble. Data Encoding Phase Reversal Keying (PRK) utilizes two phases of the SUPERIOR state, SUPERIOR S1 and SUPERIOR S2, which are 180 out of phase with one another, to modulate the encoded data. This modulation technique is more robust than the ASK technique, because it allows the P485 to correlate and track each symbol rather than just those encoded as SUPERIOR states. Figure 9 shows an example of PRK. July 1998 11 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC 100 usec Phase 2 Chirp (S2) 114 usec Superior ASK 114 usec Inferior ASK 100 usec Phase 1 Chirp (S1) 100 usec Phase 2 Chirp (S2: 180 degree reversal) Preamble Phase Message Body Phase Figure 9. ASK and PRK Data Patterns July 1998 12 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC Timing Diagrams All timing values are referenced from the 50% mid-point between VDD and VSS. All output timings assume 50 pF load at the pin. trst RST_N TS tdis ILD tdis RO tdis Figure 10. Reset Timing Table 1. Reset Timing Parameters Symbol trst tdis Notes: 1. Parameter Reset Pulse Width Output Disable Time Min 300 3 Typ - Max 20 Units ns ns Notes 1 Signals are forced asynchronously to their inactive state on reset. July 1998 13 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC XIN tck12 4MHZ td tpwh tck4 td tpwl Figure 11. 4 MHz Clock Output Timing Table 2. 4 MHz Clock Timing Parameters Symbol td tck12 tck4 tpwh tpwl Notes: 1. 2. 3. Parameter Output Delay Input Clock Period Output Clock Period Pulse Width High Pulse Width Low Min 3 83.288 249.75 - Typ 83.333 250 125 125 Max 20 83.375 250. 25 - Units ns ns ns ns ns Notes 1 2 3 3 Oscillator frequency is 12 MHz 0.05%. Clock frequency is 4 MHz 0.1%. Assumes XIN is 12 MHz 0.05%. Actual pulse width is determined by duty cycle of the oscillator. July 1998 14 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC DI Start tbit D0 D1 D2 tbyte tchar D3 D7 / D8 Stop tbit tgap Figure 12. DI Input Timing Table 3. DI Input Timing Parameters Symbol tbit tgap tbyte tchar Notes: Parameter Bit Pulse Width Baud Rate Inter-Character Gap Inter-Character Bits Byte Length Character Length 1. Min 101.01 9300 0 0 8 10 Typ 104.16 9600 <1 - Max 107.52 9900 430.08 4 9 11 Units us baud us bits bits bits Notes 1 1 Corresponds to one bit width. July 1998 15 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC RO Start tbit D0 D1 D2 tbyte tchar D3 D7 / D8 Stop tbit tgap Figure 13. RO Output Timing Table 4. RO Input Timing Parameters Symbol tbit tgap tbyte tchar Notes: Parameter Bit Pulse Width Baud Rate Inter-Character Gap Inter-Character Bits Byte Length Character Length 1. Min 100.00 9576 0 0 8 10 Typ 104.16 9600 - Max 104.42 10000 469.89 4.5 9 11 Units us baud us bits bits bits Notes 1 1 2 2 2. Corresponds to one bit width. RO output is nominally 9600 baud. If the received baud rate exceeds 9600 baud, the receiver will adjust RO's output baud rate to prevent internal buffer overflow. Inter-character gap on RO's output is a function of the received character rate and transmitted inter-character gap. Transmitted baud rates of less than 9600 baud increases the inter-character gap on RO's output. Transmitted baud rates of greater than 9600 baud decreases the intercharacter gap on RO's output. July 1998 16 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC +5V R12 60882 REV.1 K R5 10K R13 10 C7 33PFC C4 0.1UFZ 1 2 3 R9 1K R15 24K D A 33 C5 0.1UFZ D1 BAV99 C16 3300PFX L3 180UH C15 .01UFX 4MHZ ILD VSSD XIN XOUT VDDD NC DI WL RO VSSD TP0 VDDA SI C1 C2 SO VSSA RST* TS 20 19 18 17 16 15 14 13 12 11 VAA R8 180 VAA OUTPUT FILTER / TRANSIENT PROTECTION VAA Q2 MMBT3904 Y1 12 MHz 4 PREAMP R4 1M 5 6 7 Q3 MMBT3904 R14 47 R10 1.2K C18 1500PFX C17 3300PFX L4 120UH D2 1N5819 L1 1.8UH NLC D3 1N5819 D5 P6KE10A LINE COUPLING C10 1 TX1 2 C22 1.0UF, 63V 4 P10 HOST DC BUS D6 P6KE24C P11 C6 33PFC P1 8 9 C9 680PFX C8 680PFX 1.0UF, 63V D4 P6KE10A 3 INPUT FILTER VAA 12:12 HOST 4MHz P2 10 U1 SSC_P485 R6 10K HOST GND 1 2 3 4 5 6 7 8 VSS VDD VSS TXO VSS VDD TP0 TS NC VSS NC CEXT NC BIAS VDD TXI 16 15 14 13 12 11 10 9 HOST ILD P3 C1 1.0UFX BUFFER Q1 MMBT3904 L2 180UH C11 0.1UFZ DC BUS INTERFACE R7 75K, 1% +5V HOST DI P4 C2 0.1UFZ R3 1K HOST RO P5 U2 SSC_P111 VAA P7 HOST WL P6 C3 220PFC R2 13K R11 100 C13 3300PFX C12 1500PFX R1 510 C19 22UF,25V C14 0.1UFZ C21 22UF,25V HOST +5V P8 HOST VAA C20 33UF,25V P9 HOST RST* HOST GND TRANSMIT PREFILTER HOST INTERFACE POWER SUPPLY Figure 14. P485 Reference Application July 1998 17 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC SSC P485 Mechanical Specifications Dimensions in Inches Figure 15. 20-Pin SOIC Package Outline July 1998 18 Revision 5 24000828 ADVANCE INFORMATION SSC P485 PL Transceiver IC Ordering Information SSC P485 PL Transceiver IC 5100 West Silver Springs Boulevard Ocala, Florida 34482 Phone: (352) 237-7416 Fax: (352) 237-7616 Internet http://www.intellon.com ftp://ftp.intellon.com (c)Intellon Corporation, 1998. Intellon Corporation reserves the right to make changes to this data sheet without notice. Intellon Corporation makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Intellon Corporation assumes no liability arising out of the application or use of any product or circuit. Intellon Corporation specifically disclaims any and all liability, including without limitation consequential or incidental damages. July 1998 19 Revision 5 24000828 ADVANCE INFORMATION |
Price & Availability of P485
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |